This invention relates to a correlator and method for correlating, and more particularly, to a correlator and method of correlating in phase (I) and quadrature (Q) signal data.
Correlators are often used in many different types of processing systems, such as a tracking and location system, where time and angle of arrival have to be determined. Other information can be correlated, such as video and radar signals, as well as tracking and location information. In one proposed tracking and location system, a chirp waveform can be processed with an oscillator and associated circuits to increase the bandwidth. A correlator can be used as a matched filter for processing the chirp waveform, including the step of demodulating the chirp waveform.
One type of complex correlator has a basic function. It compares a reference to an incoming signal and gives a complex correlation. In emerging technologies, it is desirable to handle high data rates, such as four megabits a second. Correlators, however, become much more complicated when a quadrature input is required, e.g., an I and Q input, not just a real input. For example, a video correlator may have a channel data in and quantisizes a number of bits and correlates 1,000 samples of single points. It is necessary, however, when quadrature inputs are used to perform a cross correlation, which increases complexity. It is necessary to compare complex reference points to incoming data and determine a value, and then correlate more data again, such as 250 nanoseconds later.
Typically, larger correlators run slower. When correlators at a very low data rate, it is possible to take the data in and calculate thousands of point correlations. The time involved is extensive. These prior art types of correlators had difficulty reaching high rates, such as 4 Mbs. There was no optimal solution found between parallel and serial data flow, nor the loading of references.
Additionally, prior art correlators typically cannot be cascaded. Cascading correlator chips is relevant for complex correlators that have I and Q quadrature channels. Having these two channels will usually double the size of the gates and increase the complexity of multiplexers. As to the cascading of multiple correlator chips in the past, if a correlator had 1,000 samples and it was necessary to have 2,000 samples, a designer would take two 1,000 sample correlators, input the data, and then run through a delay with a shift register or RAM based delay and feed it to two chips. Additionally, reference data were not efficiently loaded, and storage of data and references using traditional shift register flip flops was not efficient.
It is therefore an object of the present invention to provide a correlator having an increased flexibility that replaces a traditional shift register flip-flop and allows enhanced loading of I and Q reference data.
In accordance with one aspect of the present invention, the correlator includes a circuit for serially receiving in phase (I) and quadrature (Q) signal data along parallel I and Q signal channels and converting the data to blocks of n bit parallel I and n bit parallel Q signal data. At least one programmable 5 read only memory (PROM) stores the I and Q reference data. A circuit is connected to the at least one programmable read only memory for receiving the I and Q reference data from the programmable read only memory along I and Q reference channels and converting the I and Q reference data to n bit parallel I and n bit parallel Q reference data upon power up of the correlator. A memory circuit receives and stores within each respective parallel I and Q signal channel a current block of n bit parallel I and n bit parallel Q signal data and the immediately previously received blocks of n bit parallel I and n bit parallel Q signal data.
In still another aspect of the present invention, a data bus receives the n bit parallel I and Q reference data and the n bit parallel I and Q signal data. The data bus has n parallel paths extending therefrom. A circuit is positioned along each parallel path extending from the data bus for receiving the n bit parallel I and Q signal data and n bit parallel I and Q reference data and correlating the respective I and Q reference data with a one bit shifted version of the respective n bit parallel I and Q signal data from an adjacent previous path to produce a correlated I component signal output and a correlated Q component signal output.
In still another aspect of the present invention, the correlator comprises at least one serial-to-parallel conversion register positioned within each I and Q reference channel that serially receives the respective I and Q reference data and converts reference data to respective n bit parallel I and n bit parallel Q reference data within respective I and Q reference channels. Also, at least one serial-to-parallel conversion register is positioned within each I and Q signal channel and receives the respective I and Q signal data and converts the respective I and Q signal data to respective n bit parallel I and n bit parallel Q signal data within respective I and Q signal channels.
In still another aspect of the present invention, at least one random access memory is positioned within each of the I and Q signal channels and receives sequences of n bit parallel I and n bit parallel Q reference data within respective I and Q signal channels based on predetermined clock cycles. An address controller can generate a signal for selecting an n bit word to be written to when loading n bit parallel I and Q signal data to respective I and Q signal channels.
In still another aspect of the present invention, the circuit positioned along each parallel path of correlating further comprises a multiplexer having I and Q channel outputs and an n bit Wallace Tree Adder connected within each of the I and Q channel outputs. The Wallace Tree Adder includes means for computing a count based on the number of bits that are set out of n bits.
In still another aspect of the present invention, the RAM that is part of the signal path forms a part of a circular buffer circuit positioned within each parallel I and Q signal channel. Each circular buffer circuit receives respective n bit parallel I and n bit parallel Q signal data within the respective I and Q signal channel. The circular buffer circuit can include a random access memory that receives the respective current block of n bit parallel I and Q signal data and overwrites the previous respective block of n bit parallel I and Q signal data. A multiplexer and first and second registers store the respective current and previous blocks of n bit parallel I and Q signal data.
In a method aspect of the present invention, the method correlates a signal having in phase (I) and quadrature (Q) signal components and comprises the steps of serially receiving in phase (I) and quadrature (Q) signal data along parallel I and Q signal channels. The method also comprises the step of converting the data to blocks of n bit parallel I and n bit parallel Q signal data. I and Q reference data are stored within a programmable read only memory (PROM).
The method also comprises the step of converting the I and Q reference data stored within the programmable read only memory to n bit parallel I and n bit parallel Q reference data upon power up of the correlator and storing the n bit parallel I and n bit parallel Q reference data within a random access memory. The method also comprises the step of storing within a memory each current n bit parallel I and n bit parallel Q signal data and an immediately previous n bit parallel I and Q signal data. A data bus receives the n bit parallel I and Q reference data and the n bit parallel I and Q signal data.
The method further comprises the step of correlating along each parallel path extending from the data bus the n bit parallel I and Q reference data with a one bit shifted version of n bit parallel I and Q signal data from the adjacent previous path to produce a correlated I signal component output and a correlated Q signal component output.